The present invention relates to a MOS dynamic RAM Cell consisting of a single MOSFET and a single MOS capacitor.
Recent trends in semiconductor memory devices are higher integration and larger capacity. Particularly, MOS dynamic RAMs having memory cells each consisting of a MOSFET and a MOS capacitor have achieved the highest integration because of the type of memory cell. A 256-Kbit MOS dynamic RAM is already commercially available, and a 1-Mbit RAM has been developed in a laboratory. A MOS dynamic RAM in which a MOSFET is arranged vertically with respect to a semiconductor substrate and a pn junction between the semiconductor substrate and a drain region of the MOSFET is used as a capacitor is disclosed in Japanese Patent Publication (KOKOKU) No. 58-34946. However, in this device, a soft error due to .alpha.-rays easily occurs because the capacitor is formed in the semiconductor substrate. In other words, .alpha.-particles radiated from radioactive elements such a U, Th and the like in a package material generate electron-hole pairs in the semiconductor substrate. Electrons undesirably reach a pn junction which constitutes the capacitor, thus erasing storage data. In an integrated chip, a contact area between the bit line and the channel region is required for each memory cell. In addition, a field region for element isolation is also required for each memory cell.